The present invention relates generally to integrated circuit modeling and optimization techniques. More specifically, the present invention relates to the design of analog/RF and digital circuits based on device level simulation models incorporating process and environmental variations. Merely by way of example, the invention has been applied to statistical analysis and optimization of analog/RF and digital circuits. The methods and techniques can be applied to other applications as well such as MEMS design, radiation hardened circuit design, statistical process control, and the like.
As IC technologies are scaled to finer feature sizes (e.g. deep sub-micron feature sizes) and circuit applications move to higher frequency bands (e.g. radio frequency (RF) applications), analog/RF circuit design faces a variety of challenges. For example, non-ideal effects such as parasitic coupling and process variations may adversely impact circuit performance. As a result, in some cases, to account for these non-ideal effects, the analog/RF circuit design becomes more complicated, increasing the difficulty of understanding the design as well as increasing the difficulty of the design process. Accordingly, manual design of present analog/RF circuits is generally a time-consuming process that requires a significant measure of design experience.
An approach to optimizing analog/RF circuit designs is to apply stochastic search algorithms (e.g. simulated annealing and genetic programming) to circuit sizing. These stochastic search algorithms are generally extremely slow and result in expensive computation costs.
Another approach to optimizing analog/RF circuit designs is to perform circuit sizing based on response surface modeling. According to some of these methods, circuit performance metrics are simulated at a number of sampling points over a local design space. The sampling points are fit as either linear or quadratic polynomial response surface models. These response surface models are used in either a linear or quadratic programming process to determine the optimal design in the local design space. As will be evident to one of skill in the art, linear polynomial response surface models may not be sufficiently accurate and quadratic polynomial response surface models may produce non-optimal solutions when local minimums are present. In addition, building the conventional quadratic models generally requires a great number of sampling points and solves a great number of unknown coefficients, yielding an extremely expensive computation cost.
To obtain globally optimized solutions, another approach used in some analog circuit optimization processes is the approximation of the analog circuit specifications by posynomial functions. As such, analog circuit sizing tasks can be formulated as a geometric programming problem. Given a fixed circuit topology, the circuit performance metrics are approximated as posynomial design equations and then optimized by geometric programming. This process provides a globally optimal solution for the analog circuit sizing problem. However, the conventional geometric programming approaches require the creation of the posynomial design equations by hand. A drawback of such manually derived equations is that this manual process applies various simplifications and may ignore many second-order effects. In order to improve the posynomial modeling accuracy, several algorithms have been proposed to build quadratic posynomial models using numerical simulation data. However, these conventional methods are computationally expensive.
Building conventional quadratic response surface models, both polynomial and posynomial models, requires simulation at a large number of sampling points, resulting in expensive computation costs. Moreover, building these conventional quadratic response surface models entails the solution of a large number of unknown coefficients, also resulting in expensive computation costs. As a result of these drawbacks, conventional response surface modeling approaches are generally only applicable to small and medium size circuit designs.
In some circuit optimization models, process and environmental variations are included in the simulation. Process and environmental variations may be modeled as either corners or random variables. The inclusion of these process variations generally results in an additional increase in the computation cost necessary to determine an optimal solution.
FIG. 1 is a simplified flowchart of a conventional circuit design process. As illustrated in FIG. 1, a design specification is received (110), generally from a circuit designer. The design specification will include a number of parameters, including gain, bandwidth, distortion, power, area, and the like. An initial global search is performed (112) to provide an initial circuit design. Generally, the initial global search utilizes an equation-based optimization process in which selected design variables are assigned optimized values. As will be evident to one of skill in the art, design variables include length and width of metal-oxide semiconductor field effect transistors (MOSFETs), length and width of resistors, lengths and widths of capacitors, and the like. Often, the equation-based optimization processes use simplified equations that can introduce error into the search results.
Local tuning (114) is performed to determine an optimal circuit design based on the results of the initial global search. As discussed above, this step is typically a simulation-based optimization that is either oversimplified to produce a tractable problem or prohibitively expensive in computational terms. Generally, for optimization processes that simulate complex circuit designs, in order to produce results at a reasonable computational cost, non-ideal effects (e.g. parasitic coupling) and process/environmental variations are either not included or included at only a basic level. A final design is produced (116) that may not be globally optimized (e.g. models fit using quadratic polynomials that result in non-convex optimization and local minimums) and/or may not incorporate expected process/environmental variations. Therefore, there is a need in the art for improved methods and apparatus for optimizing the values of design variables for integrated circuit elements in view of process and environmental variations.